1. Field of the Invention
This invention generally relates to protection for nonvolatile memory devices and, more particularly, to a dual thin oxide Electric Static Discharge (ESD) network for nonvolatile memory applications.
2. Description of the Related Art
The primary requirement of a nonvolatile memory is that it retains its information after the power is removed from the circuit. Metal Oxide Semiconductor (MOS) transistors have been used for this purpose since they have a high gate impedance to ground, and they thus are capable of long-term charge retention, provided that the oxide is of adequately high quality. One such conventional nonvolatile memory structure is a p-channel MOS field effect transistor (PFET) with a floating polysilicon gate. A more advanced memory cell design consists of a stacked polysilicon gate structure, where an upper electrode serves as the control gate.
Nonvolatile memory operation can also be based on the principle of tunneling through a thin oxide. Typically, this is done by arranging for a small portion of the floating gate to be placed over a thin oxide (100-200 .ANG.) through which tunneling can take place. Among these type of devices are programmable read only memories (PROMS). A specific type of PROM are the electronically erasable programmable read only memory (EEPROM or E.sup.2 PROM) devices which can be erased on a bit-by-bit basis and reprogrammed. These nonvolatile memory devices require electrostatic discharge (ESD) protection.
Prior nonvolatile memory devices have been built using 3.3 V complementary MOS (CMOS) technology. However, a more recent demand for a 12 V power pin for nonvolatile random access memory (NVRAM) programming has arisen in the RAM industry, which has created a need for a ESD protection network that will not over voltage the NVRAM circuitry.